Drain Induced Barrier Lowering (DIBL) Effect on the Intrinsic Capacitances of Nano-Scale MOSFETs
نویسندگان
چکیده
This paper presents a physical explanation of MOSFET intrinsic gate to drain capacitance (CGD) going negative due to Drain Induced Barrier Lowering (DIBL) effect. For the sub-90nm MOS devices, DIBL effect may be dominant enough to guide CGD to negative if de-embedded from parallel extrinsic overlap, outer and inner fringing capacitances. The possibility of this phenomenon is evident from the results of our 2-D TCAD simulations of conventional bulk MOS structure. However negative capacitances lead to non-convergence issue in circuit simulators and need to be bounded in MOS devices compact models.
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